Successive approximation analog to digital converter
The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance. Internal reference voltages of nominally 2.56 V or AV CC are provided on-chip.
SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER HOW TO
See the paragraph “ADC Noise Canceler” on page 227 on how to AVCC must not differ more than ☐.3 V from V CC. The ADC has a separate analog supply voltage pin, AVCC. A block diagram of the ADC is shown in Figure 107. The ADC contains a Sample and Hold circuit which ensures that the input voltage to theĪDC is held at a constant level during conversion. If 200x gain is used, 7-bit resolution can be expected.
If 1x or 10x gain is used, 8-bit resolution can be expected. Seven differential analog input channels share a common negative terminal (ADC1), while any other ADC input can be selected as the positive input terminal. Two of the differential inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. The device also supports 16 differential voltage input combinations. The single-ended voltage inputs refer to 0 V (GND). The ADC is connected to an 8-channel Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the pins of Port F. The ATmega128 features a 10-bit successive approximation ADC. 2-wire Serial Interface Characteristics.Simple Assembly Code Example for a Boot Loader.Reading the Fuse and Lock Bits from Software.Setting the Boot Loader Lock Bits by SPM.Multi-master Bus Systems, Arbitration and Synchronization.16-bit Timer/Counter Register Description.16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3).8-bit Timer/Counter0 with PWM and Asynchronous Operation.Timed Sequences for Changing the Configuration of the Watch Dog Timer.Using all 64KB Locations of External Memory.